Power-Up Delay for Retiming Digital Circuits

Retiming is sometimes used to optimize gate-level sequential designs. This technique allows memory elements to be moved across combinational elements. Unfortunately, retiming may cause the environment of a design to wait for a few additional clock cycles after power-up to guarantee the same behavior as the original design. Leiserson and Saxe [1] presented a bound on this number of clock cycles; in this paper, we tighten this bound. A smaller bound allows the environment of a design to wait for fewer clock cycles.